Bu er Minimization in Pass Transistor Logic

With the shrinking feature sizes and increasing transistor counts on chips, the push for higher speed and lower power makes it necessary to look for alternative design styles which o er better performance characteristics than static CMOS. Among them, pass transistor logic (PTL) circuits give great promise. Since the delay in a pass-transistor chain is quadratically proportional to the number of stages, and a signal may degenerate when passing through a transistor, bu ers are necessary to guarantee performance and restore signal strength in PTL circuits. In this paper, we rst analyze the e ects of bu er insertion on a circuit and give the su cient and necessary condition for safe bu er insertion. Then the bu er minimization problem is formulated, which asks for a minimum number of bu ers to make sure that no path has length longer than a given upper bound. Although NPhard in general, we show that, when bu ers are required on multiple fan-outs, it can be solved linearly. We also consider the case when bu ers are inverters, where phase assignment need to be done with bu er insertion. Experiments are done on MCNC logic synthesis and optimization benchmarks; compared with a level-by-level insertion, a large number of bu ers are saved.